Semiconductor devices are used in the electronics industry in various types of consumer products, such as pagers, phones, portable equipment, computers, and the like. It is desirable to minimize the size of these semiconductor devices because board space can be limited. However, for a semiconductor device having increased functionality which results in high input/output (I/O) connections, the resulting packaged device can be larger than desired. One approach to packaging devices having high I/O connections has been a package having an area array configuration, which allows higher density connections than a peripheral array configuration. Examples of area array devices are pin grid array (PGA) and ball grid array (BGA) packages. PGAs feature a multiplicity of plug-in pins arranged in an array or matrix format on the bottom of a substrate. This type of package is typically ceramic and is not a surface mount package, but PGAs can be made with printed wiring boards (PWB), such as epoxy-glass. PGAs can be surface mounted in some configurations, but reliable assembly can be complicated by variations in surface flatness of the substrate being contacted by the pins in the surface mount assembly process.
A typical BGA 120 is illustrated in FIG. 1 as prior art. BGA 120 has a semiconductor die 12 mounted to a PWB substrate 122. Die 12 is electrically connected to conductive traces (not illustrated) on the PWB substrate 122 with a plurality of wire bonds 20. A plastic encapsulant 124 encapsulates the semiconductor die 12 and wire bonds 20 on the top surface of the PWB substrate 122. The wire bonds 20 and the conductive traces (not illustrated) are electrically connected with vias or plated through-holes 140 and 141. Plated through-hole 141 is often bisected when excised from the panel in which it is manufactured as illustrated in FIG. 1. BGA 120 has a plurality of solder balls 126 arranged in an array format along a bottom surface of the PWB substrate 122. BGA 120 is a surface mount device which is more desirable in many applications. A disadvantage to a BGA is that it is usually assembled on a PWB with a junction-side-up die orientation, wherein the active surface of the die is facing away from the PWB. This orientation is thermally inefficient. The heat generated by the device usually has to be dissipated into the board since the thermal resistance of encapsulant 124 is typically too high.
In some cases, the solder connections under the die area of a junction side up BGA are used for thermal dissipation. In other instances, signal, power, or ground connections can be made underneath this die area if the substrate is multilayered. This reduces the thermal performance of the package. If all the I/O contact area under the die region is used for thermal dissipation, then the signal I/Os which could have been connected under the die must be placed on another row of contact pads in the BGA I/O matrix. This added row causes an increase in package size which is not desirable.
It is preferable to design a package with a die down (or junction side down) configuration so that the heat generated during device operation can be dissipated into the ambient environment. Additionally, a heat sink may be attached to the backside of the package to provide a direct heat flow path away from the device and the PWB. Such a package is illustrated in FIG. 2 as prior art. In FIG. 2, BGA 130 is in a die down configuration, wherein the semiconductor die 12 is mounted to a copper plane 134 that is laminated to a PWB substrate 132. PWB substrate 132 has a cavity to accommodate the die 12. Again, wire bonds 20 electrically connect the die 12 to the substrate 132. A plastic encapsulant 124 encapsulates the die 12 and the wire bonds 20 on a bottom surface of the PWB substrate 132. A plurality of solder balls 126 is arranged in an array format on the bottom surface of the PWB substrate 132. However, because BGA 130 is in a die down configuration, the area underneath the die cannot be used for electrical signal, power, or ground connections. Thus, in an effort to improve the thermal performance of the device 130, the size of the substrate must be increased to accommodate the routing of traces for solder ball connections.
It is desirable to package a semiconductor die using an area array configuration in which an entire surface of the packaged device can be used for I/O connections without degrading thermal management of the device.